Conventionally, one stage of a sampling/holding S/H circuit is used as a circuit for sampling and holding analog signals. In the one stage of the sampling/holding circuit, a received input is sampled and held periodically. In other words, the sampling/holding S/H operation comprised of a sampling S period and holding H period that follows the sampling period is repeated for each S/H period. Consequently, when the S/H operation is executed repeatedly, the S/H period comprised of the S period and the H period is continuous in time in such a form that after one period ends, the next period starts. In that case, it is necessary to shorten each S/H period in order to speed up the S/H operation. However, in the case of shortening the holding H period, insufficient voltage convergence occurs during the holding period. On the other hand, although the voltage convergence during the holding period can be accelerated by increasing the current flowing to the amplifier concerned with the holding operation, the power consumption is increased due to the aforementioned current increase.
Also, in a pipeline A/D converter, one S/H circuit is arranged in each of the multiple A/D converting stages connected continuously in a longitudinal direction. When each converting stage receives the output as a result of the conversion processing including the S/H operation of the S/H circuit in the previous converting stage, it executes a converting operation including another S/H operation with respect to the received output. If this operation is viewed from the angle of S/H operation alone, each S/H operation occurs continuously in time in the same way as the aforementioned one-stage S/H circuit with the next S/H period starting after the end of the previous period. Consequently, the conversion time of an A/D converter including multiple A/D converting stages is basically affected by the period calculated by multiplying the S/H period by the number of stages. This causes the same problem as increasing the speed for the aforementioned one-stage S/H circuit when the speed of the conversion of the entire A/D converter is increased by shortening the S/H period in each converting stage.